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Logical Design 1 / Logical Design of Digital Computers

- Curs-
      anul I CE

Cap. 0: Introduction (2019)

Cap. 1: Boolean Algebra (2019)

Cap. 2: Switching Functions(2019)

Cap. 3: Logic Forms(2019)

Cap. 4: Systems and Signals(2019)

Cap. 5: Combinational Logic Circuits(2019)

Cap. 6: Combinational Logic Circuits in MSI(2019)

Cap. 7: Classical Synthesis of CLC(2019)

Cap. 8: Memory Devices(2019)

Appendix A1-A3

Appendix A7

Table for MEM 32x8

- Laborator-

Laboratory activities rules

Lab. 1: Presentation of the laboratory

Lab. 2: AND, OR and NOT functions properties

Lab. 3: NAND, NOR and XOR functions properties

Lab. 4: Logic Forms

Lab. 5: Scheme editing and simulation using Xilinx and ModelSim

Lab. 6: Minimisation of switching functions

Anexa: Utilizarea mediului integrat XILINX ISE 9.2 in modelarea schemelor cu circuite logice

Situaţie laborator CEN1.1 (pg. 1), CEN1.2 (pg. 2), CEN1.3 (pg. 3): (click aici)

LD1 Exam - Results - 28.01.2020 (Grupa CEN1.1-pg. 1, Grupa CEN1.2-pg. 2, Grupa CEN1.3-pg. 3 ):(click aici)

Titular disciplină - Ş.l. dr. ing. Eugen Dumitrascu
Aplicaţii - dr. ing. Felicia Panea
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