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Logical Design 2 / Digital Systems Design

- Curs-
      anul I CE

Cap. 0: Introduction (2020)

Cap. 1: Introduction to VHDL (2020)

Cap. 2: VHDL Statements (2020)

Cap. 3: CLC Synthesis Using VHDL (2020)

Cap. 4: Sequential Logic Circuits (2020)

Cap. 5: Sequential Logical Circuits in MSI (2020)

Cap. 6: Programmable Logic Devices (2020)

Cap. 7: Synthesis of FSM (2020)

Cap. 8: Synthesis of digital Systems (2020)

Probleme Seminar

Table for MEM 32x8

- Laborator -

Lab. 0: CLC folosind Schematic

Lab. 1: Multiplexoare logice

Lab. 2: Decodificatoare si demultiplexoare

Lab. 3: Sumatoare binare

Lab. 4-5-6: Codificatoare de prioritate / Complementator fata de 1 / Generator bit de paritate

Lab. 7: Modelarea si sinteza bistabilelor (Flip-flops)

Lab. 8: Modelarea si sinteza registrelor

Lab. 9: Modelarea si sinteza numaratoarelor si divizoarelor de frecventa

Lab. 10: Modelarea si sinteza FSM

Lab. 11: Modelarea si sinteza Sistemelor Digitale folosind ASM (exemple din curs: slides 26-29)

Anexa 1: Introducere in modelarea VHDL

Anexa 2: Utilizarea mediului integrat XILINX ISE 9.2

Anexa 3: TTL Logic Modules


Situatie finala laborator Grupa CEN1.1 (pg. 1), Grupa CEN1.2 (pg. 2) si Grupa CEN1.3 (pg. 3): (click aici)

LD2 Exam Results - 19.06.2019 (Grupa CEN1.1-pg. 1, Grupa CEN1.2-pg. 2, Grupa CEN1.3-pg. 3):(click aici)

Titular disciplină - Ş.l. dr. ing. Eugen Dumitraşcu
Ing. Felicia Panea
Obs: Pentru a deschide fisierele PDF, trebuie instalat Adobe Acrobat Reader v.7 (download Adobe home page)