Skip to main content.

This page’s menu:

Digital Systems Design

- Laboratory description -
      Ist year, CE
     


1. Logic multiplexersrequirements
2. Logic decodersrequirements
3. CLC synthesis using MUXes and DECsrequirements
4. Binary addersrequirements
5. Registersrequirements
6. Counters and frequency dividersrequirements
7. Classical synthesis of SLNsrequirements
8. ASM diagrams utilisationrequirements
9. VHDL 
10. VHDL 
11. VHDL 
12. VHDL 
13. Laboratory redoing 
14. Laboratory test 

- Exam -


The students must pass a written examination.
In order to be allowed to enter the written examination, the minimum lab grade must be 5. In order to achieve a minimum grade of 5 for the labs, the presence is mandatory. There will be 12 laboratories, the 13th week is dedicated to redoing missed laboratories (a maximum of two) and the last to the laboratory test.


- Laboratory situation -

1) 10105 B - 10106 B - laboratory situation - renewed 23.05.2012
Discipline titular - Ş.l. Dr. Eng. Eugen Dumitraşcu
Asist. Drd. Ing. Dan Ovidiu Andrei
Asist. Drd. Ing. Adrian Neaţu